Version 1.1 Update: Canonical HMAA Formal Verification Artifacts Version 1.1 adds the canonical formal-verification artifacts for the Hierarchical Multi-Level Authority Allocation architecture. The added materials include the TLA+ finite-state-machine specification, reduced and operational-bound TLC configuration files, complete and partial TLC execution logs, original supporting documentation, detailed reproduction instructions, and an archival correction note. The completed canonical TLC run used MaxTick=8, MaxDwell=8, OscMaxTransitions=3, and OscLockoutTicks=4. Model checking completed without a counterexample, generating 26,397,356 states and identifying 23,748 distinct reachable states at complete-search depth 9. The operational-bound configuration did not complete within the available computational budget. The archived execution excerpt documents more than 165 million generated states and 131,490 distinct states at the cutoff. Earlier figures stating 48,751 reachable states and search depth 51 could not be reproduced from the archived specification and are superseded by the canonical results included in this version. DEPOSIT_NOTE.md and REPRODUCE_verification.md document the correction, execution environment, exact commands, property coverage, vacuity limitations, and remaining verification work. Record Description This record contains a technical report and reproducible artifact package for the Authority-Governed Assured Autonomy Rover Testbed, a research platform designed for autonomous systems operating under degraded and adversarial conditions. The testbed integrates three governance architectures: SATA, Sensor Trust Assessment HMAA, Hierarchical Multi-Level Authority Allocation CARA, Context-Aware Recovery Architecture These components form a unified pipeline for trust-aware decision-making, authority computation, and adaptive recovery under uncertainty and attack scenarios. The artifact package includes: Full system architecture and formal methodology Interactive governance simulator with fault-injection scenarios Complete hardware reference design, blueprint, schematic, and bill of materials Electrical connection graph Component-level system configuration Physical-platform assembly guide Source repository containing the implementation, formal models, and supporting materials Canonical HMAA TLA+ and TLC formal-verification artifacts Validation status: Technology Readiness Level: TRL 3–4 for simulation and specification work Governance architectures evaluated through 350 structured simulation runs across seven fault-injection scenarios Hardware design and construction artifacts completed Physical assembly and experimental validation remain future work Canonical HMAA formal-verification evidence added in Version 1.1 This artifact is intended for reproducibility, system-design inspection, simulation-based evaluation, and formal-verification review. It does not represent a fully hardware-validated or operationally deployed system. All materials are released under the Creative Commons Attribution 4.0 International License.