wafer-proc-sim is an open-source framework for physics-informed simulation of silicon carbide (SiC) wafer processing, covering the full semiconductor manufacturing pipeline from front-end dicing and grinding through Fab process equipment models to back-end packaging and test. The framework extends the TMCMC Bayesian inference and multiscale FEM methodology developed in Nishioka et al. (2026, doi:10.5281/zenodo.18790007) to the semiconductor domain, integrating Gaussian process (GP) surrogate models for calibration against experimental dicing data. It includes quantitative physics models for semiconductor equipment manufacturers (ASML EUV, TEL, Disco, Lasertec, Advantest, Lam Research, AMAT, KLA), device manufacturers (TSMC, Intel, Samsung, SK Hynix, Nvidia), and emerging technologies including vertically integrated mega-fabs (Terafab), silicon spin qubit fabrication for quantum computing, and hyperscaler custom AI ASIC supply-chain analysis. All models are validated against peer-reviewed literature with 66 physics-constrained unit tests.