We report a preliminary hardware study of an N = 12 periodic transverse-field Isingmodel (TFIM) executed on a native 12-qubit heavy-hex plaquette of IBM Heron hardware.By mapping the logical periodic boundary condition directly onto the processor’s nativetopology, we eliminate routing overhead and obtain zero-SWAP transpilation on the selectedcycle.The study combines exact local diagonalisation, symmetry-preserving ring ansätze, bound-before-transpile compilation, native fractional-gate execution, and single-PUB estimation ofthe Hamiltonian energy together with parity and local symmetry witnesses. We comparedeeper (p = 3) and shallower (p = 2) variational settings under matched hardware-orientedexecution conditions, including fractional-gate transpilation and dynamical decoupling whereapplicable.Our principal empirical result is a consistent depth-versus-noise tradeoff: a shallowerp = 2 circuit produced better hardware energy and parity than a deeper p = 3 circuit,despite the deeper ansatz being superior in ideal local simulation. We interpret this asevidence that, on present-generation noisy hardware, reduced interaction cost and topology-matched execution can outperform greater variational expressivity.We do not claim ground-state certification from the present runs. Instead, we presentthese results as preliminary empirical evidence of topology-matched cyclic symmetry sig-natures under noise, together with a reproducible workflow for native heavy-hex plaquetteexperiments.