Intellectual Property Core Of Axi Memory Controller For Fpga

This paper proposes an implementation of AXI 2.0 protocol which removes the limitation of communication architecture, which would otherwise reduce the speed of data transfer in System on chip. We have also implemented DDR3 controller which was then interface with AXI 2.0 protocol. In comparison with earlier generations, DDR1/2 SDRAM, DDR3 SDRAM is a higher density device and achieves higher bandwidth due to the further increase of the clock rate and reduction in power consumption. Proposed protocol was synthesized on Xilinx 13.1 and simulated using Modelsim 6.5e.

Keywords

AXI, DDR3, Modelsim, Xilinx.

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