Power dissipation has become a critical design concern in modern VLSI systems due to aggressive device scaling and the resulting increase in leakage currents. The CMOS input-inverter multiplexer (MUX) is widely employed as a fundamental building block in configurable and control-oriented digital circuits. However, its continuous operation leads to considerable static power consumption, particularly in deep-submicron technologies. This paper presents the analysis of a power-efficient CMOS input-inverter MUX incorporating the Leakage Control Transistor (LECTOR) technique. In the proposed architecture, LECTOR transistors are integrated into the inverter stage of the CMOS input-inverter MUX to effectively suppress subthreshold leakage currents during both idle and switching conditions. Key performance parameters, including transient response, slew rate, and power dissipation, are evaluated and compared with those of a conventional CMOS input-inverter MUX. Simulation results demonstrate a significant reduction in power dissipation, achieving operation in the sub-microwatt range while maintaining stable transient characteristics. Although a moderate degradation in slew rate is observed due to the inclusion of additional leakage control transistors, the overall performance trade-off remains acceptable for low-power and energy-constrained applications. Consequently, the proposed CMOS input-inverter MUX with LECTOR technique is well suited for low-power programmable logic and configuration circuits in modern VLSI systems.