The pipelined processor architecture is the best way to increase instruction-level parallelism, and thus,understanding its operation is one of the keys in computer architecture learning. To help with the leaningprocess, we have devised a series of pipeline simulation methodologies. This article presents one of them –a simulation methodology of hazard detection and forwarding in MIPS32 pipelined floating-point units.Our implementation approach is using the Node-RED programming environment, an event-driven dragand-drop system for designing data flows with business logic. In addition, to implement sophisticated operations not supported by Node-RED, we also employ WebAssembly code and the Rust language. Wesimulate not only the standard 5-stage pipelined MIPS ISA but also pipelined (addition, subtraction, andmultiplication) and unpipelined (division) floating-point operations. Our study focuses mainly on hazarddetection, which is required to ensure program correctness, as well as forwarding used to improve systemperformance. Lastly, we design a dashboard interface to visually represent the pipeline stages and CPUstatus during execution. Using the dashboard interface, MIPS32 machine code can be loaded into oursimulator from hexadecimal text files. We verified that our simulator is handling hazard detection andforwarding correctly. A screenshot of the dashboard interface is included that shows all the stages offloating-point pipelines.