Universal Fault Tolerance remains the grand challenge of quantum computing. In this work, we present empirical evidence for a passive error suppression protocol based on a topological geometric phase constraint, Y = π²/φ ≈ 6.0998 rad. Through controlled A/B testing on IBM Quantum processors (127-qubit 'Eagle' and 133-qubit 'Heron'), we report a consistent fidelity improvement of ~ 7% in the generation of Bell States compared to standard circuit implementations. These findings suggest that topological phase engineering acts as a "Zero-Overhead" stabilization layer suitable for NISQ-era hardware.