
This work presents a comprehensive statistical analysis of MOSFET mismatch using a large 48×48 n‑channel MOSFET transistor matrix fabricated in a 0.18 µm CMOS process. The study evaluates local variability through extensive IdVg measurements, extracting key parameters such as threshold voltage (Vth), current factor (β), and effective channel length (Leff). Multiple extraction techniques, including Y‑function, linear extrapolation, and the shift‑and‑ratio method, are compared for robustness and statistical significance. Results show that mismatch distributions follow a Student‑t behavior, secondary size effects influence Pelgrom‑type scaling, and accurate Leff estimation requires constrained ΔVth ranges. The findings support improved compact modeling, SPICE simulations and variability‑aware IC design.
SPICE, MOSFET, Mismatch, Design, IC
SPICE, MOSFET, Mismatch, Design, IC
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