This list shows the main core changes since the last release. See the project's changelog for more information. :bug: Bug Fixes fixed bug in MTIME comparator logic (interrupt condition mtime >= mtimecmp was not always evaluated correctly) fixed CPU's IRQ prioritization: (re-)enter debug mode interrupts have to be evaluated before all other interrupts fixed missing IRQ signal assignments (MSW and XIRQ) in AXI4-lite top wrapper :bulb: Updates and New Features :warning: split processor-internal memory VHDL sources (IMEM and DMEM) into separated files (#151): entity-only (rtl/core/neorv32_*mem.entity.vhd) and default architecture-only (rtl/core/mem/neorv32_*mem.default.vhd) :warning: Zifencei extension is now required for the on-chip debugger; executing fence.i without having the Zifencei extension enabled will now cause an illegal instruction exception :warning: major change of low-level hardware access (memory-mapped registers) PR #158: now using struct-based access concept (IO module = struct, interface registers = members of struct) instead of #define single-pointers, format: NEORV32_<module_name>.<register_name> renamed all control registers and bits from *CT* to *CTRL* added sw/lib/include/neorv32_legacy.h compatibility layer (maps deprecated "defines" to according structs, provides old control register/bit names) :warning: reworked CPU trap/exception system (in order to comply with RISC-V specs.): removed non-maskable interrupt (NMI, top signal nm_irq_i) reworked CPU trap prioritization (sync exceptions before debug mode enter exceptions before async exceptions) RISC-V interrupts (MTI, MSI, MEI) are now high-level-triggered and require to stay asserted until they are explicitly acknowledged started porting the task management system to PyDoit PR #110 misa, mip and mtval CSRs are read-only; however, write accesses to these CSRs do not raise an illegal instruction exception (anymore) added menvcfg[h] CSRs (only available if U ISA extension is enabled; not used yet - hardwired to zero, but required by RISC-V spec.) reworked CPU/software handshake of external interrupt controller XIRQ to avoid "external IRQ -> CPU IRQ" race conditions if CPU_CNT_WIDTH generic (actual width of [m]cycle and [m]instret counters) is less than 64 the remaining bits are now just hardwired to zero ignoring any write access instead of causing an exception :heavy_check_mark: Pull Requests and Issues Merged pull requests: #150 [sim] create subdir 'simple', avoid making a local copy of 'sw' and 'sim' #151 [rtl/core] split dmem/imem entities and architectures to separated files #152 Adding NEORV32 Qsys/Platform Designer component and AvalonMM Master Interface wrapper #154 fix typo wb_mem_a.cyc on sim example #156 [docs/userguide] update section 'Simulating the Processor' #158 rework low-level hardware access #159 [setups/osflow/filesets] do not provide default NEORV32_MEM_SRC, require it to be explicitly set #160 add pydoit to custom dockerfiles #161 [containers] update from Debian Buster to Debian Bullseye #162 [doit] add initial doit file; add task DeployToGitHubPages #163 [doit] add task Documentation #164 [doit] add task RunRISCVArchitectureTests #165 [doit] add task BuildAndInstallSoftwareFrameworkTests #166 docs: datasheet: soc_sysinfo: fix NEORV32_SYSINFO.SOC bits description Closed issues: #153 simulation cycle signal of instruction memory