
A parameterized, area-efficient Verilog hardware implementation of the ChaCha20 stream cipher, supporting ChaCha8, ChaCha12, and ChaCha20 variants. This release includes synthesizable RTL, testbenches validated against RFC 8439, synthesis scripts, performance analysis, reproducibility artifacts, and a technical paper.
If you use OpenSiliconHub's ChaCha20 hardware core, please cite this release.
cryptography, ASIC, hardware security, open-source hardware, ChaCha20, ARX cipher, hardware implementation, Verilog, FPGA, stream cipher
cryptography, ASIC, hardware security, open-source hardware, ChaCha20, ARX cipher, hardware implementation, Verilog, FPGA, stream cipher
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