Linear-feedback shift register (LFSR) counters have been shown to be well suited to applications requiring large arrays of counters. These counters can improve the area and performance compared with existing designs. However, significant logic is required to decode the count order of LFSR into binary order which takes additional logic circuitry. This paper presents a Multistage LFSR counter design which uses LFSR counters as well as binary counters. Combination of these two counters gives a better improvement in terms of area while maintaining the delay and power same like existing counter. Multistage LFSR counter is implemented in this paper on Xilinx 14.7 version.