Real-time image processing is a critical requirement in applications such as autonomous vehicles, medical imaging, industrial inspection, and surveillance. Conventional CPU and GPU platforms often fail to meet stringent latency and power constraints due to their sequential execution models and high energy demands. Field Programmable Gate Arrays (FPGAs) provide a promising alternative by leveraging hardware-level parallelism, low latency, and reconfigurability. This paper presents the design and implementation of an FPGA-based image processing system capable of performing edge detection and noise reduction in real-time. A combination of Sobel edge detection and Gaussian filtering algorithms were implemented in Verilog HDL on a Xilinx Artix-7 FPGA. The design was simulated, synthesized, and experimentally validated with live video input. Results indicate that the proposed system achieves 60 fps image processing with an average latency of 12 ms per frame, consuming only 3.5 W of power compared to 65 W on GPU implementations. The findings demonstrate the effectiveness of FPGAs in embedded image processing applications, while highlighting trade-offs in resource utilization and scalability