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The main objective of project is to design and verify different operations of Arithmetic and Logical Unit (ALU). We have designed an 32 bit ALU which accepts two 32 bits numbers and the code corresponding to the operation which it has to perform from the user. The ALU performs the desired operation and generates the result accordingly. The different operations are arithmetical, the coding was written in VHDL and verified in I-Sim. The waveforms were obtained successfully. After the coding was done, the synthesis of the code was performed using Xilinx-ISE.
logic unit, arithmetic unit, shift unit, arithimatic and logic unit.
logic unit, arithmetic unit, shift unit, arithimatic and logic unit.
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