This paper demonstrates the design and optimization of a Multiplier using pass transistor logic with half and full adders in 90 nm and 45 nm CMOS technology. The design methodology utilizes fewer transistors and low-power pass transistor logic to improve system efficiency. Implementation and simulation proved these designs to be superior than traditional CMOS designs in terms of area, delay, power dissipation, and energy efficiency. Optimized adders in the multiplier framework thus provide compact, power efficient multiplier design. A comparison to conventional designs shows significant reductions of power consumption, transistor count and delay and is therefore attractive for low-power, high-performance applications. This work contributes to VLSI design by addressing the major speed, area, and power trade-offs in digital systems. The optimized Multiplier is best suited for modern-day applications such as image and signal processing. The application area focuses on high-performance, high-energy efficiency, and clearly points out the advantages pass transistor logic can provide during digital circuit design to innovatively develop low-power, fast multipliers.