Ensuring the functional correctness of hardware circuits is essential for estab-lishing trust. Formal verification methods such as model checking and assertion-based verification, while widely used, are inherently limited in expressivity andscalability. These limitations prevent them from bridging the semantic gap be-tween low-level hardware implementations and high-level specifications, posingchallenges for comprehensive verification on complex circuits. This thesis addresses these challenges by developing a scalable proof infra-structure tailored for hardware verification. Specifically, it enhances the existingKôika hardware description language by introducing an improved compiler fron-tend that facilitates the processing of parametric actions. Furthermore, it proposesa new proof infrastructure that formalizes Hoare logic within Kôika’s semantics,enabling structured and modular reasoning about hardware behaviors. These contributions advance the modular verification of hardware circuits,overcoming the scalability limitations of conventional verification approaches.Future research directions include extending this framework to incorporateseparation logic, thereby addressing the frame problem, and evaluating its applic-ability to larger hardware descriptions, such as a RISC-V implementation.