A programmable intermediate frequency (IF) receiver is proposed, employing a sampler, time-varying capacitor, and switched-capacitor integrator. It realizes high-order finite impulse response (FIR) low-pass or bandpass filtering (BPF) and frequency translation with harmonic rejection (HR). The receiver's center frequency and bandwidth (BW) can be independently programmed across the Nyquist zone. The primary focus is on balancing filter stopband rejection with harmonic, image, and alias rejection in a prototype 28 nm CMOS chip design. This work is also the first to address and quantify the adjacent and alternate adjacent channel aliasing in filtering by aliasing filters. The center frequency and BW of the receiver can be programmed to 0-1 GHz and 8-25 MHz, respectively. The receiver achieves a wideband impedance matching S 11 50 dB stopband attenuation at 1 × BW offset, HR, image rejection (IR), and 50 dB in-band (IB) alias suppression. The I and Q receivers use only a single fixed 1 GHz clock frequency to achieve all the functionality and consume 73.6 mW.