
This artifact contains the modified gem5 cycle-accurate simulator and compartmentalized MiBench benchmarks for the secure cache isolation mechanism: SCC as outlined in the paper "Secure Caches for Compartmentalized Software". Follow the directions of the baseline gem5 system (also m5ops.h for the pseudo-instructions) to compile the simulator in your system. We also included the compartmentalized MiBench environment that we used in our experiments. The Makefiles of MiBench benchmarks we use have already been modified to be used with m5ops.h pseudo-instructions. Just change your home directory name from "/home/kerem" to your work directory name to use the modified MiBench makefiles and the runmi.py python script. After changing your home directory in runmi.py, use this script to generate permission tables and experiment results of your own. You can also use our m5ops.h pseudo-instructions to compartmentalize your custom programs as well. Follow the gem5 tutorial on m5ops.h to compile C/C++ programs with pseudo-instructions: m5_start_secure_proc(int compart_name); m5_end_secure_proc(int compart_name); m5_horiz_compart(int compart_name); Due to licensing restrictions, we cannot share the compartmentalized SPEC'17 benchmarks.
TEEs, Secure Caches, Side-Channel Attacks, Hardware Security, Software Compartmentalization, Cache Isolation, Computer Architecture
TEEs, Secure Caches, Side-Channel Attacks, Hardware Security, Software Compartmentalization, Cache Isolation, Computer Architecture
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