Flip flops are essential in digital circuits for data storage and synchronization. Adding synchronous reset enhances reliability by enabling controlled data clearing. Designed in standard CMOS technology, our D flip flop integrates logic gates and feedback loops for stable operation. Reset occurs synchronously with external clock cycles. Simulations and analysis validate setup time, hold time, propagation delay, and power consumption against benchmarks, affirming robust performance. Investigations into input conditions and clock frequencies highlight design stability. This research advances digital circuitry, demonstrating synchronous reset's benefits in achieving reliable data storage and controlled resetting, essential for integrated and efficient digital systems. This study focuses on the design and validation of a D flip-flop with synchronous reset, leveraging standard CMOS technology and Cadence Virtuoso tools.