The adder is acknowledged as the fundamental component in various arithmetic and logical operations. In efforts to enhance operational efficiency, the Carry Select Adder (CSLA) has been devised. By integrating multiple high-speed adder logics within a conventional CSLA framework, operational speed is further enhanced. This study presents the design of a hybrid CSLA that amalgamates the advantages of both Kogge Stone Adder and Look Ahead Adder (CLA) methodologies to achieve superior performance. Kogge Stone Adder, distinguished for its rapid carry generation, is incorporated to bolster speed. Concurrently, Look Ahead Adders are strategically deployed in the initial stages of the enhanced adder to capitalize on their computational prowess, particularly beneficial for smaller bit numbers. A 64-bit hybrid CSLA is realized on the Xilinx Spartan 6 FPGA development board. The resultant modified hybrid carry select adder demonstrates notable improvements in speed and energy efficiency, surpassing conventional carry select adder implementations.