This paper presents the design and implementation of a 4-bit synchronous sequential up/down counter using JK flip-flops. The counter operates in both ascending and descending modes, displaying output on two 7-segment displays. The design process includes state diagram creation, JK state table derivation, and Boolean expression optimization using Karnaugh maps. Implemented in Logisim, the final circuit demonstrates a functional counter capable of displaying hexadecimal values from 0 to F. This work illustrates the effective use of JK flip-flops in synchronous counter design for digital applications.