A 16-bit pipelined analog-to digital device (ADC) is intended during this paper. The pipelined design realizes the high-speed and high-resolution. To cut back some complexities of flash ADC pipeline ADC is employed. The standardization schemes of pipelined ADC limit absolute and relative accuracy. Deviations in residue electronic equipment gain results because of low intrinsic gain of transistors, and mismatching between all the capacitors of capacitance 1pF lead to each deviations in residue electronic equipment gain and DAC nonlinearity in a much pipelined ADC. To image the planet, a low-power CMOS image sensing element array is needed within the vision processor. The image sensing element array is usually fashioned through pin diodes and analog to digital device (ADC). To attain low power acquisition, a low-power mid-resolution ADC is important. Digital correction permits conjointly to use terribly low power dynamic comparators. The multiplying D/A converters (MDACs) utilize a changed collapsed dynamic electronic equipment .In this allows to the employment of dynamic amplifiers in a very pipeline ADC. Additionally, the dynamic electronic equipment offers each clock measurability and high-speed operation even with a scaled offer voltage. exploitation the higher than techniques, a sixteen bit epitome ADC achieves a conversion rate of 407 MS/s with a offer voltage of 1.2 V. Therefore, the mixture of interpolated pipeline design and dynamic residue amplifiers demonstrates the practicability of ultra-low voltage high-speed analog circuit style. To implement the total system a low-power and tiny size capacitance worth sensing readout circuit is needed. Also, it's to be integrated along with the back-end low-power current-mode ADC on constant chip. The low-power current-mode ADC has been designed and unreal with TSMC 0.18um CMOS technology. Within the simulation result, the facility consumption for 16-bit ADC was ninety 1.9 microwatt, with an influence offer of 1.2 V.