Design Of A Quinary To Residue Number System Converter Using Multi-Levels Of Conversion

The objective of this paper is to present the design of a Quinary to Residue Number System (RNS) converter over the Quinary moduli set {23, 24, 25} by using Multi levels of MVL to RNS converters. This method will lead to minimize the number of used logic elements (gates, adders,..) hence reducing the propagation delay, decreasing the chip density and complexity comparing to other methods those are used in binary to RNS conversion.

Keywords

Multiple Valued Logic (MVL), Residue Number System (RNS), Quinary Logic (Quin), Quinary Full Adder, QFA, Quinary Half Adder, QHA.

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