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DSP has become a key component, in many of the user, communications, medical and industrial products which implement the processing of signal using microprocessors, Field Programmable Gate Arrays (FPGAs), Custom ICs etc. Fast Fourier transform (FFT) has an important role in many digital signal processing (DSP) systems. E.g., in orthogonal frequency division multiplexing (OFMD) communication systems, FFT and inverse FFT are needed. The OFMD technique has become a widely adopted in several wireless communication standards. When operating in wireless environment the devices is usually to be powered using battery and, therefore, an energy efficient FFT implementation is needed. Signal processing concepts are often presented in a very mathematical and abstract format. This can discourage students from further exploration because of the apparent irrelevance to real world problems. In this paper, VLSI architecture for FFT algorithm is proposed. This architecture is authorized in Verilog language .Behavior simulation is done by using the Model Sim 6.0. PAR Simulation can be done by using the synthesis Xilinx ISE 10.1.