In digital circuits multiplication is a fundamental operation, extensively utilized in various computational tasks. The efficiency and performance of the multiplier circuit significantly impact the overall system performances, especially in applications demanding high-speed computation with minimal power consumption. This study presents a comparative analysis between two distinct implementations of Radix-4 8*8 Booth multiplier employing different adder architectures: Ripple carry adder and Modified Square Root Carry select adder. Multiplier with modified square root carry select adder reduced critical path delay (CPD), power delay product (PDP) and area delay product(ADP). Generic process design kit (gpdk) of 45nm technology is used for design and implementation using Cadence software. Keywords:- Booth Multiplier; Carry Select Adder; Critical Path Delay; Power Delay Product; Area Delay Product; Cadence.