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Concurrent Testing Of Adc For Embedded System

Authors: Y.B.Gandole;

Concurrent Testing Of Adc For Embedded System

Abstract

{"references": ["Actel Corporation, SmartFusion Intelligent Mixed-Signal FPGAs:\nInnovative Intelligent Integration, 2010; www. actel. com/ FPGA/ Smart\nFusion", "I.Voyiatzis, A. Paschalis, D.Gizopoulos,N.Kranitis, and C.Halatsis, \"A\nConcurrent BIST Architecture Based on a Self-Testing RAM\", IEEE\nTransactions on Reliability, vol.54, No.1, 2005, pp. 69-78.", "C. Stroude, J. Morton, T. Islam and H. Alassaly, \"A mixed-signal built-in\nself-test approach for analog circuits\", Southwest Symposium on Mixed-\nSignal Design, Las Vegas, USA, 2003, pp. 196-201.", "R. Frohwerk, \"Signature Analysis: A New Digital Field Service\nMethod\",Hewlett Packard J., vol. 28, No 9, May 1977, pp. 2-8.", "G. Starr, J. Qin, B. Dutton, C. Stroud, F. Dai and V. Nelson \"Automated\ngeneration of built-in self-test and measurement circuitry for mixedsignal\ncircuits and systems,\" Proc. IEEE Int. Symp. on Defect and Fault\nTolerance in VLSI Systems, 2009, pp. 11-19.", "R. Sharma and K. Saluja, \"Theory, analysis and implementation of an\non-line BIST technique,\" VLSI Design, vol. 1, no 1, 1993, pp. 9-22.", "I. Voyiatzis, A. Paschalis, D. Gizopoulos, C. Halatsis, F. Makri, and M.\nHatzimihail, \"An input vector monitoring concurrent BIST architecture\nbased on a precomputed test set,\" IEEE Trans. Computers, vol. 57, no.\n8, 2008, pp. 1012-1022.", "I. Voyiatzis, D. Gizopoulos, and A. Paschalis, \"An input vector\nmonitoring concurrent BIST scheme exploiting \"X\" values,\" 15th IEEE\nInt. On-Line Testing Symposium, 2009, pp. 206-207.", "Y.-S. Wang, J.-X.Wang, F.-C.Lai and Y.-Z. Ye, \"A low-cost BIST\nscheme for ADC testing\", Shanghai, China, VI Int. Conf. on ASIC, vol.\n2, 2005, pp. 665-668.\n[10] D. Lee, K. Yoo, K. Kim, G. Han and S. Kang, \"Code-width testingbased\ncompact ADC BIST circuit\", IEEE Trans. on Circuits and\nSystems-II: Express briefs, vol. 51, No 11, 2004, pp. 603-606.\n[11] G. Wu, J. Rao, A. Ren and M. Ling, \"Implementation of a BIST scheme\nfor ADC test\", V Int. Conf. on ASIC, Beijing, China, vol. 2, 2003, pp.\n1128-1131.\n[12] A. Gookin, \"A fast reading high resolution voltmeter that calibrates\nitself automatically\", Hewlett Packard J., vol. 28, No 6, 1977, pp. 2-10.\n[13] V. Kneller, \"Measurement, control and other processes: to the problem\nof knowledge systematization\",Cavtat-Dubrovnik, Croatia, XVII IMEKO\nWorld Congress, 2003, pp. 1119-1124.\n[14] G. D'Antona and A. Ferrero, Digital Signal Processing for Measurement\nSystems, Springer Science + Business Media Inc., Berlin, 2006.\n[15] J. Wakerly, Error Detecting Codes, Self-Checking Circuits and\nApplications, Elsevier North-Holland, New York, 1978.\n[16] V. Geurkov, L. Kirischian, and V. Kirischian \"Signature Testing of\nAnalog-to-Digital Converters\". Proceedings of the 19th IMEKO World\nCongress: Fundamental and Applied Metrology, Lisbon,"]}

Compaction testing methods allow at-speed detecting of errors while possessing low cost of implementation. Owing to this distinctive feature, compaction methods have been widely used for built-in testing, as well as external testing. In the latter case, the bandwidth requirements to the automated test equipment employed are relaxed which reduces the overall cost of testing. Concurrent compaction testing methods use operational signals to detect misbehavior of the device under test and do not require input test stimuli. These methods have been employed for digital systems only. In the present work, we extend the use of compaction methods for concurrent testing of analog-to-digital converters. We estimate tolerance bounds for the result of compaction and evaluate the aliasing rate.

Keywords

Analog-to Digital Converter, Concurrent Testing, Embedded system

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