This paper analyzes the Signal Integrity (SI) performance of thin-film microstrip lines (TFMSL), in view of their use in future communication systems, operating at unprecedented high I/O data rates (over 30 Gb/s) and high frequency (over 60-GHz). Here, various chip-level structures with coupled TFMSL are analyzed, with a special focus on mismatching and coupling associated with different choices of geometry. A frequency domain analysis is carried out using two commercial simulation tools to estimate insertion loss, crosstalk, and mode conversion. A high-speed digital link is then simulated in the time domain to evaluate the SI performance in terms of eye-diagram metrics, over a wide range of data-rate values, from 1 to 100 Gbit/s. The effect of the geometry and coupling is analyzed, and design maps are obtained, suggesting trade-off optimized choices of data-rate values, given the line geometries.

This work was supported by the European Metrology Programme for Innovation and Research (EMPIR), under the 20IND03 - FutureCom project. EMPIR programme is co-financed by the Participating States and from the European Union's Horizon 2020 Research and Innovation Programme. Funder ID: 10.13039/100014132 , Grant no: 20IND03