The semiconductor industry is moving to highly regular designs, or 1D gridded layouts, to enable scaling to advanced nodes, as well as improve process latitude, chip size and chip energy consumption. The fabrication of highly regular ICs is straightforward. Poly and metal layers are arranged into 1D layouts. These 1D layouts facilitate a two-step patterning approach: a line-creation step, followed by a line-cutting step, to form the desired IC pattern (See Figure 1). The first step, line creation, can be accomplished with a variety of lithography techniques including 193nm immersion (193i) and Self-Aligned Double Patterning (SADP). It appears feasible to create unidirectional parallel lines to at least 11 nm half-pitch, with two applications of SADP for pitch division by four. Potentially, this step can also be accomplished with interference lithography or directed self assembly in the future. The second step, line cutting, requires an extremely high-resolution lithography technique. At advanced nodes, the only options appear to be the costly quadruple patterning with 193i, or EUV or E-Beam Lithography (EBL). This paper focuses on the requirements for a lithography system for "line cutting", using EBL to complement Optical. EBL is the most cost-effective option for line cutting at advanced nodes for HVM.