In this paper, we propose a dynamically run-time reconfigurable power aware cryptographic processor for secure autonomous encryption. The design proposes the implementation of a dynamically reconfigurable AES cryptography process on an FPGA. The proposed design encompasses a microarchitecture which is variously power, latency, and throughput optimized via hardware acceleration and partial reconfiguration by a multi-level autonomic controller and a data router to enable tradeoffs under changing operational requirements within resource constraints. The multi-level controller decides on the appropriate configuration based on varying operational workloads to characterize the effect that time-varying task parameters have on the hardware architecture, to enable a run-time tradeoff of performance and resources usage (Key length, computational efficiency, latency and throughput).