The application of existing reliability test standards, based on Si technology, to SiC power MOSFET reliability qualification can in some cases result in ambiguous test results. Depending on the exact measurement procedure, a given device stress tested under identical conditions may either pass or fail. The large variations observed in I D -V GS characteristics, and accompanying shift in threshold voltage (V T ) and change in leakage current, are likely due to the complex time, temperature, and bias dependent nature of the charging and discharging of significant numbers of near-interfacial oxide traps (and possibly mitigated by the movement of mobile ions) which are not present in Si power devices. The variation in V T following a high temperature gate-bias (HTGB) stress is shown to be dependent on the measurement delay time, sweep direction, and temperature. Negative gate-bias temperature stress results show that device reliability may be limited due to increased drain leakage current in the OFF-state, which is caused by large shifts in V T depending on the gate-bias stress time, bias magnitude, and stress temperature. In addition, positive gate-bias stressing at elevated temperature may increase power dissipation in the ON-state.