Total-dose and SEU characterization of 0.25 micron CMOS/SOI integrated circuit memory technologies

descriptionPublicationkeyboard_double_arrow_right Article 01 Dec 1997Publisher:Institute of Electrical and Electronics Engineers (IEEE)Journal:IEEE Transactions on Nuclear Science, volume 44, pages 2,134-2,139 (issn: 0018-9499, eissn: 1558-1578,

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Authors: Brothers, C.; Pugh, R.; Duggan, P.; Chavez, J.; Schepis, D.; Yee, D.; Wu, S.;

doi: 10.1109/23.659028

Total-dose and SEU characterization of 0.25 micron CMOS/SOI integrated circuit memory technologies

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Abstract

Total-dose and single-event-effect radiation characterization of 0.25 micron test macro SRAMs fabricated at IBM's East Fishkill research foundry in un-hardened bulk and un-hardened partially-depleted SOI silicon, are reported. The design and fabrication process were optimized for high-performance and short access time using supply voltages of 2.5 V for the 64 K-bit and 1.8 V for the 144 K and 288 K-bit test macro SRAMs.

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United States Air Force Research Laboratory
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