The design of pipelined Fast Fourier transform (PFFT) in modern communication systems provides an efficient way for computation of FFT with better area utilizing hardware architecture. Previously, the radix-22 had been used only for single path delay feedback architectures. Later with many types of research works the radix 22 was extended to multi-path delay commutator (MDC) architectures. This paper presents area optimization of parallel pipelined radix-22 feed forward Fast Fourier transform (PPFFT) architecture. This architecture is provided for parallelism value 4 and 16 sample points and the area of proposed PFFT is compared with other PFFT (feed forward) architectures using the same synthesis tool and FPGA. The comparison shows that the proposed architecture exhibits better area optimization.