On Designing Testable Reversible Circuits Using Gate Duplication

descriptionPublicationkeyboard_double_arrow_right Part of book or chapter of book , Conference object , Other literature type 01 Jan 2013Publisher:Springer Berlin Heidelberg

Authors: Joyati Mondal; Debesh Kumar Das; Dipak Kumar Kole; Hafizur Rahaman 0001; Bhargab B. Bhattacharya;

doi: 10.1007/978-3-642-42024-5_38

On Designing Testable Reversible Circuits Using Gate Duplication

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Abstract

Design of reversible logic circuits has received considerable attention in recent times for their potential use in implementing quantum computers. In this paper, it is shown that in an (n×n) reversible circuit implemented with k-CNOT gates, addition of only two extra inputs along with at most 5 k-CNOT gates per gate can yield an easily testable design. The modified design admits a universal test set of size (n + 2) that detects all SMGFs, PMGFs, and detectable RGFs in the circuit.

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11 Research products, page 1 of 2

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