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System-level simulator for the W-CDMA low chip rate TDD system

Authors: null Sung Ho Moon; null Jae Hoon Chung; null Jae Kyun Kwon; null Suwon Park; null Dan Keun Sung; null Sungoh Hwang; null Junggon Kim;

System-level simulator for the W-CDMA low chip rate TDD system

Abstract

A system-level simulator for the W-CDMA low chip rate TDD system is developed. This simulator considers multi-cell and multi-user environments and SIR-based power control. For accurate and reliable results, inner-cell and outer-cell interference is modeled by chip-level spreading and an SIR estimation scheme is used. From this simulator, system-level performance is evaluated in terms of the received SIR distributions for downlink and uplink. The degradation probability is also introduced as a QoS indicator at system level.

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selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
1
Average
Average
Average
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