The IEEE 802.3ae task force adopted a 64b/66b encoding scheme for 10 Gb Ethernet, where each 64-bit word is scrambled using a self-synchronous scrambler with polynomial x58+x39+1. Because of its acceptable run length and low overhead, the 64b/66b encoding is also a candidate encoding scheme for high speed inter-shelf, chip-to-chip, and backplane interconnections. While scrambling facilitates data synchronization, a self-synchronous scrambler has the disadvantage of duplicating errors, i.e. every transmission error results, after descrambling, in two or more additional errors. There is, however, no provision in the IEEE 802.3ae for single or multiple error correction of 64b/66b encoded links. We propose a fast and efficient error-correction scheme that can be used in conjunction with the 64b/66b encoding in products where intra-board or inter-shelf interconnections of high speed elements are required. The proposed algorithm takes into account the duplication of errors through computing the position of such errors, and generating a syndrome table accordingly. The algorithm also accounts for errors which cross the codeword boundaries entering into the next codeword (carry over errors). The proposed algorithm is 64-bit aligned, compatible with the structure of 10 GbE specified in the IEEE 802.3. Moreover, the algorithm is general; it is applicable to M-bit encoded links, where M is any arbitrary number of bits in an encoded codeword, and the self-synchronous scrambler could be of any polynomial. We specify the functional blocks of the algorithm including error control blocks at the transmitter and receiver, the buffer structure to store the code words, the CRC computation algorithm, a syndrome table, and a comparator to compare the calculated syndrome with the syndrome table in order to detect and correct single bit errors. We also perform a simulation with exhaustive test vectors (all possible errors) to demonstrate that the algorithm detects and corrects all single-bit errors on a 64/66 bit encoded links