At advanced nodes, CMOS logic is being designed in a highly regular design style because of the resolution limitations of optical lithography equipment. Logic and memory layouts using 1D Gridded Design Rules (GDR) have been demonstrated to nodes beyond 12nm.[1-4] Smaller nodes will require the same regular layout style but with multiple patterning for critical layers. One of the significant advantages of 1D GDR is the ease of splitting layouts into lines and cuts. A lines and cuts approach has been used to achieve good pattern fidelity and process margin to below 12nm.[4] Line scaling with excellent line-edge roughness (LER) has been demonstrated with self-aligned spacer processing.[5] This change in design style has important implications for mask making: • The complexity of the masks will be greatly reduced from what would be required for 2D designs with very complex OPC or inverse lithography corrections. • The number of masks will initially increase, as for conventional multiple patterning. But in the case of 1D design, there are future options for mask count reduction. • The line masks will remain simple, with little or no OPC, at pitches (1x) above 80nm. This provides an excellent opportunity for continual improvement of line CD and LER. The line pattern will be processed through a self-aligned pitch division sequence to divide pitch by 2 or by 4. • The cut masks can be done with “simple OPC” as demonstrated to beyond 12nm.[6] Multiple simple cut masks may be required at advanced nodes. “Coloring” has been demonstrated to below 12nm for two colors and to 8nm for three colors. • Cut/hole masks will eventually be replaced by e-beam direct write using complementary e-beam lithography (CEBL).[7-11] This transition is gated by the availability of multiple column e-beam systems with throughput adequate for high- volume manufacturing. A brief description of 1D and 2D design styles will be presented, followed by examples of 1D layouts. Mask complexity for 1D layouts patterned directly will be compared to mask complexity for lines and cuts at nodes larger than 20nm. No such comparison is possible below 20nm since single-patterning does not work below ~80nm pitch using optical exposure tools. Also discussed will be recently published wafer results for line patterns with pitch division by-2 and by-4 at sub-12nm nodes, plus examples of post-etch results for 1D patterns done with cut masks and compared to cuts exposed by a single-column e-beam direct write system.