
While hardware generators have drastically improved design productivity, they have introduced new challenges for the task of verification. To effectively cover the functionality of a sophisticated generator, verification engineers require tools that provide the flexibility of metaprogramming. However, flexibility alone is not enough; components must also be portable in order to encourage the proliferation of verification libraries as well as enable new methodologies. This paper introduces fault, a Python embedded hardware verification language that aims to empower design teams to realize the full potential of generators.
CAV 2020: 32nd International Conference on Computer-Aided Verification
Software Engineering (cs.SE), FOS: Computer and information sciences, Computer Science - Software Engineering, Hardware Architecture (cs.AR), Computer Science - Hardware Architecture, Article
Software Engineering (cs.SE), FOS: Computer and information sciences, Computer Science - Software Engineering, Hardware Architecture (cs.AR), Computer Science - Hardware Architecture, Article
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| influence This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically). | Top 10% | |
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