BLAKE is a cryptographic hash function which was one of the 5 finalists in the SHA-3 competition and although it ultimately lost to Keccak the algorithm was very well received for its both cryptographic strength and performance. In this paper we propose particular modifications in hardware implementation of the cipher which employ built-in FPGA block RAM modules in order to eliminate involved distribution of message bits among cipher rounds. The idea is tested on 4 different architectures: the standard iterative one and three loop-unrolled organizations with 2, 4 and 5 rounds instantiated in hardware. Parameters of the architectures implemented with two popular FPGA families – Spartan-3 and Spartan-6 – indicate that substantial reductions in design size can be achieved also with some (albeit not so spectacular) improvements in speed.