This paper describes the design and LSI implementation of a dynamic SIMD/MIMD mode switching processor core (the XC core) for embedded real-time image recognition systems. The XC core supports both a highly parallel SIMD and a medium parallel MIMD architecture, which are suitable for exploiting the large amount of data-level and task-level parallelisms respectively that exist in most image recognition algorithms. Each PE of the SIMD is extended to support a low cost 6-way VLIW data-path and uses an efficient autonomous inter-PE data transfer, to improve the SIMD performance. By employing a hardware resource reuse strategy whereby four PEs of the SIMD are reconfigured into one PU (Processing Unit) of the MIMD, the hardware overhead for supporting both modes is reduced to merely 15% of the area increase compared with either a SIMD only or MIMD only design. LSI implementation of the 32 PE or 8 PU XC core resulted in a die size of 7.7mm2 in 55nm CMOS process and achieved a peak performance of 42.5GOPS, while dissipating 421mW at 133MHz and 1.2V. Compared with an existing SIMD only design, the normalized PE performance for processing regular SIMD image tasks was improved by a factor of 4, the while performance for processing irregular MIMD image tasks has been improved by a factor of 14.