This paper presents a 16-bit AES architecture for low power and high bit rate applications. The novelty is in breaking the original 32-bit boundary based AES algorithm into a scalable architecture to work with 8-bit and 16-bit data set. 8-bit architecture is already developed. This new work offers a choice to the designer to use 8-bit or 16-bit algorithm for area and power efficient FPGA implementation. The novelty of the new development is still around the mix-column design. The complex matrix multiplication component and standard transformations of the 32-bit AES algorithm are transformed now to support 16-bit operations as well, simultaneously qualifying for applications requiring high data rates. The design has been further embellished by a memory based micro-programmed controller, which simplifies the control process of the algorithm and makes the FPGA platform viable for effective hardware utilization. The proposed architecture technique reuses same hardware resources for both key expansion and encryption