In the process of designing high performance microprocessors, architects and designers build processor models at varying levels of abstraction for a range of purposes. Examples of such uses are simulating and verifying the processor, predicting processor performance, and developing operating systems and applications for the processor before silicon is available. Such models can range in complexity from simple analytical performance models in spreadsheet format to the detailed design expressed in a hardware description language (HDL). Other models that fall in between on the range of complexity include instruction-accurate simulators, trace-driven performance simulators, and cycle-accurate simulators. There is usually a trade-off between runtime performance and accuracy while using these models. Developing a large number of models for a processor is an expensive proposition. Beyond the engineering resources to build the initial models, developers must verify each of the models for correctness against the design specification; they must also maintain and update the models as the design evolves. Clearly, a strategy that limits the number of models yet meets the requirements of early software developers, verification engineers, and performance analysts is desirable. During the course of the picoJava processor design, we developed a simple and effective methodology that meets the goals of both accurate performance analysis and design validation. Although we applied this technique to the picoJava processor, the technique can be applied to other processor designs.