Summary form only given, as follows. We describe an analog VLSI implementation of the ART1 algorithm (Carpenter, 1987). A prototype chip has been fabricated in a standard low cost 1.5 /spl mu/m double-mental single-poly CMOS process. It has a die area of 1 cm/sup 2/ and is mounted in a 120 pin PGA package. The chip realizes a modified version of the original ART1 architecture. Such modification has been shown to preserve all computational properties of the original algorithm (Serrano, 1994), while being more appropriate for VLSI realizations. The chip implements on ART1 network with 100 F1 nodes and 18 F2 nodes. It can, therefore, cluster 100 binary pixels input patterns into up to 18 different categories. Modular expansibility of the system is possible by assembling an N/spl times/M array of chips without any extra interfacing circuitry, resulting in an F1 layer with 100/spl times/N nodes, and an F2 layer with 18/spl times/M nodes. Pattern classification is performed in less than 1.8 /spl mu/s, which means an equivalent computing power of 2.2/spl times/10/sup 9/ connections and connection-updates per second. Although internally the chip is analog in nature, it interfaces to the outside world through digital signals, thus having a true asynchronous digital behavior. Experimental chip test results are available, which have been obtained through test equipment for digital chips.