The emerging technology of reversible circuits offers a potential solution to the synthesis of ultra low-power quantum computing systems. A reversible circuit can be envisaged as a cascade of reversible gates only, such as Toffoli gate, which has two components: k control bits and a target bit (k-CNOT), k ≥1. While analyzing testability issues in a reversible circuit, the missing-gate fault model is often used for modeling physical defects in k-CNOT gates. In this paper, we propose online design-for-testability (DFT) technique. The proposed method is an improved version of an earlier work by Kole et. al. Our method yields less overhead in terms of quantum cost as compared to the original approach. The method is advantageous for circuits where consecutive gates occur frequently with the same set of controls.