Phase Change Memory (PCM) is a promising alternative to DRAM to achieve high memory capacity at low cost per bit. Adding to its better projected scalability, PCM can also store multiple bits per cell (called multi-level cell, MLC), offering higher bit density. However, MLC requires precise sensing and control of PCM cell resistance, which incur higher memory access latency and energy. We propose a new approach to mapping and buffering data in MLC PCM to improve memory system performance and energy efficiency. The latency and energy to read or write to MLC PCM varies depending on the resistance state of the multi-level cell, such that one bit in a multi-bit cell can be accessed at lower latency and energy than another bit in the same cell. We propose to exploit this asymmetry between the different bits by decoupling the bits and mapping them to logically separate memory addresses. This exposes reduced read latency and energy in one half of the memory space, and reduced write latency and energy in the other half of memory, to system software. We effectively utilize the reduced latency and energy by mapping read-intensive pages to the read-efficient half of memory, and write-intensive pages to the write-efficient half. Decoupling the bits also provides flexibility in the way data is buffered in the memory device, which we exploit to manipulate the physical row buffer as two logical row buffers for increased data locality in the row buffer. Our evaluations for a multi-core system show that our proposal improves system performance by 19.2%, memory energy efficiency by 14.4%, and thread fairness by 19.3% over the state-of-the-art MLC PCM baseline system that does not employ bit decoupling. The improvements are robust across a wide variety of workloads and system configurations.