Maximum a posteriori (MAP) and data transition tracking loop (DTTL) synchronizers are developed for the differential phase shift keying (DPSK) scheme. In their original form, these synchronizers require substantial hardware for their realization. By some simplifications, hardware complexity can be considerably reduced. Simplified all-digital MAP and DTTL synchronizers are suggested. The hardware needed to realize these schemes is not significantly more than that required for the simple early-late scheme. Results of computer simulation studies on all-digital MAP and DTTL synchronizers are given. They not only indicate that the degradation in the bit error rate performance of the demodulator due to these synchronizers is about 0.2 dB, as compared to 1 to 2 dB for the simple early-late scheme, but also that the MAP and DTTL schemes have much lower jitter. Results of an experimental study on microprocessor-based hardware realizations of the synchronizers are given. The circuits developed are suitable for the realization of a digital IC for synchronization as well as in DPSK modems. >