Hardware-Accelerated neural network

This work presents a parametrizable design of a neural network on an FPGA, being trained previously in the CPU using backpropagation. We test different configurations and report delay, power and area.

Country

Spain

Related Organizations

Keywords

Neural networks (Computer science), Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors, :Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors [Àrees temàtiques de la UPC], Matrius de portes programables in situ, Neural Network, Field programmable gate arrays, Accelerador, Accelerator, Xarxes neuronals (Informàtica), VHDL, Xarxa Neuronal, FPGA

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