Latch-up in CMOS integrated circuits

This paper defines the latch-up failure mechanism in CMOS, analyzes methods and tools to detect it, including microscopy techniques capable of identify parasitic latch-up paths; test structures for the study of latch-up sensitivity and methods to prevent latch-up are also described.

Country

Italy

Related Organizations

University of Modena and Reggio Emilia
Italy
University of Padua
Italy

Keywords

CMOS; integrated circuits; failure analysis; failure mode; latch-up; reliability, Latch-up. CMOS. SEM Voltage Contrast.

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