
handle: 11375/23808
Electronic devices such as phones and computers use cryptography to achieve information security. However, while cryptographic algorithms may be strong theoretically, their physical implementations in hardware can leak unintentional side information as a byproduct of performing their computations. A device's security can be compromised from this leakage through side-channel attacks. Research in hardware security reveals how dangerous these attacks can be and provides security countermeasures. This thesis focuses on a category of side-channel attacks called fault attacks, and contributes a new fault attack method that can compromise a cryptographic device more rapidly than the previous methods when using practical fault injection techniques. We observe that as a circuit is further overclocked, new faults are often superimposed upon previous ones. We analyze the incremental changes rather than the total sum in order to extract more secret information. Unlike many previous methods, ours does not require precise fault injection techniques and requires no knowledge of when the internal state is in a specific algorithmic stage. Results are confirmed experimentally on hardware implementations of AES-128, 192, and 256.
Master of Applied Science (MASc)
Thesis
fault, cryptography, AES, DFA, differential fault analysis, attack, incremental fault analysis, hardware, security, side-channel, IFA
fault, cryptography, AES, DFA, differential fault analysis, attack, incremental fault analysis, hardware, security, side-channel, IFA
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