This thesis aims to address the challenge of suppressing the circulating current. Principle of operation and mathematical derivations, common control methods for inner dynamics and software/hardware algorithm implementation is presented, with focus on the control algorithm repetitive control for suppression of the circulating current. This algorithm utilizes the internal model principle for suppression of the periodic circulating current. Algorithm derivation and stability is analyzed in the discrete time domain and performance confirmed with MATLAB Simulink®. Algorithms are investigated and discussed both for sequential software implementation on embedded processor and as hardware logic implementation on FPGA. A model based design approach is used in MATLAB Simulink® to define system requirements, create the analyzed algorithms, simulate and verify the design, and automatically generate code for the system. MATLAB Embedded Coder® is used to generate C/C++ code for embedded processor implementation, while MATLAB HDL Coder® is used to generate synthesizable HDL code for IP core generation. The third party synthesis tool Xilinx Vivado Design Suite is used to interface the designed IP core into a complete processing system and implement the IP core onto a FPGA. Processor in the Loop (PIL) simulations is used to look at algorithm execution time in processor, while MATLAB and Vavado generate reports on hardware logic resource utilization and critical path estimations.