Service life assessments and reliability predictions for electronics need improvement early in the design phase to avoid the current uncertainties, inaccurate results, and poor design decisions. This research paper presents a merged probabilistic physics of failure (PoF) approach to account for the physical location of microelectronics and determine the resulting time-to-failure based on randomly placed failure mechanisms. A case study using a generic circuit card assembly and corrosion related failure mechanisms exhibits the utility of the merged probabilistic PoF approach. The results demonstrated that the location of microelectronics can impact the time-to-failure for a circuit card assembly because a failure mechanism’s probability of occurrence increases or decreases based on changes in temperature and humidity. Additional research and analysis using actual test results should be performed to verify the accuracy of the results and to account for additional failure mechanism types.

This research is supported by funding from the Naval Postgraduate School, Naval Research Program (PE 0605853N/2098). https://nps.edu/nrp

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ASN(RDA) - Research, Development, and Acquisition

Chief of Naval Operations (CNO)

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