Previous research was conducted on a Complementary Metal Oxide Semiconductor (CMOS) to determine the impact of a phenomenon known as Negative Bias Temperature Instability (NBTI). NBTI affects the operational characteristics of these devices, with a stronger effect on p-channel devices. This instability is apparent when the semiconductor is on biased, and exacerbated under thermal stress. This data is useful in determining the projected failure rate of certain submicron technologies. The previous experiment used On-the-Fly techniques at certain temperatures to measure the interface states in order to determine the susceptibility of the device under test to NBTI. In the previous research, thermal stress application was not exact. Temperature drift was observed over long range test evaluations, and subsequent NBTI data was determined unsatisfactory. In order to maintain thermal stress at a constant value during NBTI testing temperature stabilization is necessary. This paper explains the methods explored and adapted to stabilize temperature.

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http://archive.org/details/temperaturestabi109453300

US Navy (USN) author.